This invention relates generally to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs), and other high speed ICs, and more specifically, to a compliant passivated edge seal for low-k interconnect structures. This invention provides computer chips with improved mechanical integrity in the assembly and packaging, and also provides many additional advantages which shall become apparent as described below.
In semiconductor fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces, forming devices, such as transistors, capacitors and resistors. These devices are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC). The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching and planarization.
To increase throughput, a plurality of ICs are fabricated on a wafer in parallel. Thus, for example, a wafer may contain multiple IC units which have been formed on the planar surface area of the wafer. Each IC is a self contained entity surrounded by its own boundary region using orthogonal axes that are referred to as dicing channels or scribe lanes. Generally, these channels may have a width of about 50 to 100 μm. The ICs are typically separated into individual chips or “die” by cutting in this channel in a process known as “dicing” or “singulation”. Conventional dicing techniques include sawing with a diamond wheel, laser cutting, and “scribe and break”. As the dicing tool cuts or scribes the wafer, chips and cracks in the surface and substructure often result. Such cracks can propagate into critical areas within the IC in response to packaging stresses, and may cause permanent circuit failure.
To increase chip performance, wiring capacitance is reduced by changing from the industry-standard dielectric material SiO2 (having a relative dielectric constant of about 4.0) to lower dielectric constant (“low-k”) insulators surrounding the interconnects. These low-k materials come at a significant disadvantage of loss of mechanical properties such as hardness and elastic modulus, and other forms of robustness and resistance to failure due to internal and external stresses. In particular, it has become a problem to probe, dice, and package chips containing low-k insulators without causing fracture, chipping or cracking of the dielectric material, and pullout of the terminal metal pads. There is therefore a need to isolate these weak on-chip materials from the harsh external environment and stresses associated with assembly and packaging.
Typical prior art approaches have adopted a hard dielectric passivation layer such as a silicon nitride material. For example, U.S. Pat. No. 5,742,094 discloses a sealed semiconductor chip. A hermetic seal consisting of a thin SiN passivation layer and a Ni passivation layer is selectively deposited on the chip surface. It has been observed, however, that when a low-k dielectric material is used as the inter-metal dielectric within the active area of the chip, such hard passivation layers do not adequately protect the device from fracture, chipping or cracking of the dielectric material, and pullout of the terminal metal pads.
Other prior art approaches combine a hard dielectric passivation layer such as a silicon dioxide or silicon nitride with an overcoat of a more compliant material such as a polyimide. For example, U.S. Pat. No. 6,383,893 discloses a hard passivation layer (124) consisting of inorganic insulators such as SiO2 or SiN covering the wafer, and a soft passivation layer (125) consisting of polyimide overlying the hard passivation layer. U.S. Pat. No. 6,271,578 discloses a similar structure. Again, it has been observed that when a low-k dielectric material is used as the inter-metal dielectric within the active area of the chip, a hard passivation layer in contact with the active device area does not adequately protect the device from fracture, chipping or cracking of the dielectric material, and pullout of the terminal metal pads. The soft passivation layer overlying the hard passivation layer fails to alleviate this problem.
Another prior art approach disclosed in U.S. Pat. No. 5,665,655 involves the use of a crackstop structure, specifically a groove surrounding the active region on a chip. In this structure, a dielectric material (3) which can be polyimide is deposited over the substrate including the active device regions, and then a hard passivation layer (11) of, for example, silicon nitride is deposited over the structure. When the dicing operation is performed, however, the sidewalls of the chip remain in contact with the substrate material, which is typically a semiconductor material such as silicon. Microcracks occurring in silicon substrates tend to propagate very rapidly, and would therefore lead to failures in the adjacent low-k dielectric material. Thus, this structure also fails to protect the device from fracture, chipping or cracking of the dielectric material, and pullout of the terminal metal pads.
Therefore, a need remains in the art for a structure and process to isolate the weak on-chip materials from the harsh external environment and stresses associated with assembly and packaging.